View EV1HMC1118LP3D_8810940.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pr o duct overview o nline documentation design resources discussion sample & buy high isolation, silicon spdt, nonrefective switch, 9 khz to 13.0 ghz data sheet hmc1118 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features nonreflective 50 design positive control: 0 v/3.3 v low insertion loss: 0.68 db at 8.0 ghz high isolation: 48 db at 8.0 ghz high power handling 35 dbm through path 27 dbm terminated path high linearity 1 db compression (p1db): 37 dbm typical input third-order intercept (iip3): 62 dbm typical esd rating: 2 kv human body model (hbm) 3 mm 3 mm, 16-lead lfcsp package no low frequency spurious settling time (0.05 db margin of final rf out ): 7.5 s applications test instrumentation microwave radios and very small aperture terminals (vsats) military radios, radars, and electronic counter measures (ecms) fiber optics and broadband telecommunications functional block diagram 1 2 3 4 gnd gnd rfc gnd 12 11 10 9 v dd ls v ctrl v ss 5 6 7 8 gnd gnd rf2 gnd 16 15 14 13 gn d gn d rf1 gn d 50 ? 50 ? package base gnd hmc1118 12961-001 figure 1. general description the hmc1118 is a general-purpose, broadband, nonreflective single-pole, double-throw (spdt) switch in a lfcsp surface mount package. covering the 9 khz to 13.0 ghz range, the switch offers high isolation and low insertion loss. the switch features >48 db isolation, 0.68 db insertion loss up to 8.0 ghz, and a 7.5 s settling time of 0.05 db margin of final rf out . the switch operates using positive control voltage logic lines of +3.3 v and 0 v and requires +3.3 v and ?2.5 v supplies. the hmc1118 can cover the same operating frequency range with a single positive supply voltage applied and the negative supply voltage (v ss ) tied to ground and still maintaining good power handling performance. the hmc1118 is packaged in a 3 mm 3 mm, surface mount lfcsp package.
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy hmc1118 data sheet rev. 0 | page 2 of 11 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specifications ............................................................... 3 digital control voltages .............................................................. 4 bias and supply current .............................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ..............................6 interface schematics .....................................................................6 typical performance characteristics ..............................................7 insertion loss, return loss, and isolation ................................7 input compression point and input third - order intercept ...8 theory of operation .........................................................................9 applications information .............................................................. 10 evaluation pcb ........................................................................... 10 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history 1 0 / 15 rev ision 0 : initial version
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy data sheet hmc1118 rev. 0 | page 3 of 11 specifications electrical specifica tions v ct r l = 0 v / 3.3 v dc , v dd = ls = 3.3 v dc , v ss = ? 2.5 v dc , t a = 25c, 50 ? system, unless otherwise specified. table 1 . parameter test conditions/comments min typ max unit insertion loss 9 khz to 3.0 ghz 0.5 1.0 db 9 khz to 8.0 ghz 0.68 1.1 db 9 khz to 10.0 ghz 0.7 1.3 db 9 khz to 13.0 ghz 1.3 2.0 db isolation rfc to rf1/rf2 (worst case) 9 khz to 3.0 ghz 40 50 db 9 khz to 8.0 ghz 4 2 48 db 9 khz to 10.0 ghz 28 35 db 9 khz to 13.0 ghz 18 25 db return loss on state 9 khz to 3.0 ghz 26 db 9 khz to 8.0 ghz 22 db 9 khz to 13.0 ghz 9 db off state 9 khz to 3.0 ghz 26 db 9 khz to 8.0 ghz 14 db 9 khz to 13.0 ghz 5 db radio frequency ( rf ) settling time 50% v ct r l to 0.05 db margin of final rf out 7.5 s 50% v ct r l to 0.1 db margin of final rf out 6 s switching speed t rise /t fal l 10%/90% rf 0.85 s t on /t off 50% v ct r l to 10%/90% rf 2.7 s input power 1 mhz to 13.0 ghz 1 db compression (p1db) 35 37 dbm 0.1 db compression (p0.1db) 35 dbm input third - order intercept (iip3) two - tone input power = 14 dbm at each tone, 1 mhz to 13.0 ghz 62 dbm recommended operating conditions 1 positive supply voltage (v dd ) 3.0 3.6 v negative supply voltage (v ss ) ?2.75 ?2.25 v control voltage (v ct r l ) range 0 v dd v logic select (ls) voltage range 0 v dd v rf input power v dd /v ct r l = 3.3 v, v ss = ?2.5 v, t a = 85c, frequency = 2 ghz through path 35 dbm termination path 27 dbm hot switch power level v dd = 3.3 v, t a = 85c, frequency = 2 ghz 27 dbm case temperature range (t case ) ?40 +85 c 1 these are the recommended values for these parameters.
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy hmc1118 data sheet rev. 0 | page 4 of 11 digital control volt ages v dd = 3.3 v 10%, v ss = ?2.5 v 10%, t case = ?40c to +85 c , unless otherwise specified. table 2 . parameter symbol min typ max unit test condition/comments input control voltage <1 a typical low v il ?0.3 +0.8 v high v ih 2.0 v dd + 0.3 v bias and supply current table 3 . parameter symbol min typ max unit supply current v dd = 3.3 v i dd 20 200 a v ss = ?2.5 v i ss 0.5 10 a
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy data sheet hmc1118 rev. 0 | page 5 of 11 absolute maximum rat ings table 4 . parameter rating positive supply voltage (v dd ) range ?0.3 v to +3.7 v dc negative supply voltage (v ss ) range ?2.8 v to +0.3 v control voltage (v ct r l ) range ?0.3 v to v dd + 0.3 v logic select (ls) voltage range ?0.3 v to v dd + 0.3 v rf input power 1 (v dd /v ct r l = 3.3 v, v ss = ?2.5 v, t a = 85c, frequency = 2 ghz) see figure 2 to figure 4 through path 3 7 dbm termination path 28 dbm hot switch power level (v dd = 3.3 v, t a = 85c, frequency = 2 ghz) 30 dbm storage temperature range ?65c to +150c maximum reflow temperature (msl3 rating) 260c channel temperature 135c thermal resistance (channel to package bottom) through path 116 c/w terminated path 100 c/w esd sensitivity (hbm), class 2 2 kv 1 for recommended operating conditions, see table 1 . stresses at or above those listed under absolute maximum ratings may cause perma nent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating con ditions for extended periods may affect product reliability. 4 C24 C20 C16 C12 C8 C4 0 0 10 9 8 7 6 5 4 3 2 1 power (db) frequency (ghz) 12961-002 figure 2 . power derating through path 4 C24 C20 C16 C12 C8 C4 0 0.01 0.1 1 10 100 1000 power (db) frequency (mhz) 12961-004 3 4 C24 C20 C16 C12 C8 C4 0 0.01 0.1 1 10 100 1000 10000 power (db) frequency (mhz) 12961-003 4 esd caution
pr o duct overview o nline documentation design resources discussion sample & buy hmc1118 data sheet rev. 0 | page 6 of 11 pin configuration and fu nction descriptions 1 2 3 4 gnd gnd rfc gnd 12 11 10 9 v dd ls v ctrl v ss 5 6 7 8 gnd gnd rf2 gnd 16 15 14 13 gnd gnd rf1 gnd hmc1118 top view (not to scale) 12961-005 notes 1. the exposed pad must be connected to the rf/dc ground of the printed circuit board (pcb). figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1, 2, 4 to 6, 8, 13, 15, 16 gnd ground. the package bottom has an exposed metal pad that must connect to the printed circuit board (pcb) rf/dc ground. see figure 6 for the gnd interface schematic. 3 rfc rf common port. this pin is dc-coupled and matched to 50 . a dc blocking capacitor is required if the rf line potential is not equal to 0 v dc. 7 rf2 rf2 port. this pin is dc-coupled and matched to 50 . a dc blocking capacitor is required if the rf line potential is not equal to 0 v dc. 14 rf1 rf1 port. this pin is dc-coupled and matched to 50 . a dc blocking capacitor is required if the rf line potential is not equal to 0 v dc. 9 v ss negative supply voltage pin. 10 v ctrl control input pin. see table 1, table 2, and table 6. 11 ls logic select input pin. see table 1, table 2, and table 6. 12 v dd positive supply voltage pin. epad exposed pad. the exposed pad must be connected to the rf/dc ground of the printed circuit board (pcb). table 6. truth table control input signal path state ls v ctrl rfc to rf1 rfc to rf2 high low on off high high off on low low off on low high on off interface schematics gnd 12961-006 figure 6. gnd interface schematic v dd 12961-007 v ctrl figure 7. v ctrl interface schematic v dd 12961-008 ls figure 8. ls interface schematic
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy data sheet hmc1118 rev. 0 | page 7 of 11 typical performance characteristics i nsertion loss, return loss , and isolation 0 C4 C3 C2 C1 0 2 4 6 8 10 12 14 insertion loss (db) frequency (ghz) t a = C40c t a = +25c t a = +85c 12961-009 figure 9 . insertion loss vs. frequency 0 C50 C40 C30 C20 C10 0 2 4 6 8 10 12 14 return loss (db) frequency (ghz) rf1, rf2 off rfc rf1, rf2 on 12961-0 1 1 10 0 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 2 4 6 8 10 12 14 isolation (db) frequency (ghz) rf1 rf2 12961-010 11 1 2 0 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 2 4 6 8 10 12 14 isolation (db) frequency (ghz) rfc to rf1 on rfc to rf2 on 12961-012 12 1 2
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy hmc1118 data sheet rev. 0 | page 8 of 11 input compression point and input third - order intercept 40 28 30 32 34 36 38 0 13 12 11 10 9 8 7 6 5 4 3 2 1 input compression (dbm) frequency (ghz) 0.1db compression point 1db compression point 12961-013 figure 13 . 0.1 db and 1 db compression point vs. frequency 40 28 30 32 34 36 38 0 13 12 11 10 9 8 7 6 5 4 3 2 1 input compression (dbm) frequency (ghz) t a = C40c t a = +25c t a = +85c 12961-014 14 1 65 45 50 55 60 0 12 10 8 6 4 2 input ip3 (dbm) frequency (ghz) t a = C40c t a = +25c t a = +85c 12961-015 15 - 3 40 10 15 20 25 30 35 0.01 0.1 1 10 100 1000 input compression (dbm) frequency (mhz) 0.1db compression point 1db compression point 12961-016 16 01 1 40 10 15 20 25 30 35 0.01 0.1 1 10 100 1000 input compression (dbm) frequency (mhz) t a = C40c t a = +25c t a = +85c 12961-017 17 1 65 60 55 50 45 0.1 1 10 100 1000 input ip3 (dbm) frequency (mhz) t a = C40c t a = +25c t a = +85c 12961-018 18 - 3
p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy data sheet hmc1118 rev. 0 | page 9 of 11 theory of operation the hmc1118 requires a positive supply voltage applied to the v dd pin and a negative supply voltage applied to the v ss pin. bypassing capacitor s are recommended on the supply lines to minimize rf coupling. the hmc1118 can operate with a single positive supply voltage applied to the v dd pin and the negative voltage input pin ( v ss ) connected to ground ; however, some performance degradation s in the input power compression and third - order intercept can occur . the hmc1118 is controlled via two digital control voltages applied to the v c t r l pin and the ls pin. a small value bypassing capacitor is recommended on these digital signal lines to improve the rf signal isolation. the hmc1118 is internally matched to 50 ? at the rf input port (rfc) and the rf output ports (rf1 and rf2); therefore, no external matching components are required. the rf1 and rf2 pins are dc - coupled, and dc blocking capacitors are required on the rf paths if the rf potential is not equal to a common - mode voltage of 0 v . the design is bidirectional; the input and outputs are interchangeable. the ideal power - up sequence is as follows: 1. power up gnd. 2. power up v dd and v ss . the relative order is not important. 3. power up the digital control inputs. the relative order of the logic control inputs is not important . powering the digital control inputs before the v dd supply can inadvertently forward bias and damage the internal esd protection structures. 4. power up the rf input. the logic s elect (ls ) allows the user to define the control input logic sequence for the r f path selections. with the ls pin set to logic h igh, the rfc to rf1 path turn s on when v ct r l is logic low , and the rfc to rf2 path turn s on when v ct r l is logic h igh. w ith ls se t to logic l ow, the rfc to rf1 path t urn s on when v ct r l is logi c h igh , and the rfc to rf2 path turn s on when v ct r l is logic l ow. depending on the logic level applied to the ls and v ct r l pins, one rf output port (for example, rf1) is set to on mode, by which an insertion loss path provide s the input to the output. the other rf output port (for example, rf2) is then set to off mode, by which the output is isolated from the input. when the rf output port (rf1 or rf2) is in isolation mode, internally terminate it to 50 ?, and the port absorbs the applied rf signal (see table 7 ) . table 7 . switch mode operation digital control inputs signal mode ls v ct r l rfc to rf1 rfc to rf2 high low on mode. a low insertion loss path from the rfc port to the rf1 port. off mode. the rf2 port is isolation from the rfc port and internally terminated to a 50 ? load to absorb the applied rf signals. high high off mode. the rf1 port is isolation from the rfc port and internally terminated to a 50 ? load to absorb the applied rf signals. on mode. a low insertion loss path from the rfc port to the rf2 port. low low off mode. the rf1 port is isolation from the rfc port and internally terminated to a 50 ? load to absorb the applied rf signals. on mode. a low insertion loss path from the rfc port to the rf2 port. low high on mode. a low insertion loss path from the rfc port to the rf1 port. off mode. the rf2 port is isolation from the rfc port and internally terminated to a 50 ? load to absorb the applied rf signals.
pr o duct overview o nline documentation design resources discussion sample & buy hmc1118 data sheet rev. 0 | page 10 of 11 applications information evaluation pcb generate the evaluation pcb used in this application with proper rf circuit design techniques. signal lines at the rf port must have 50 impedance, and the package ground leads and backside ground slug must be connected directly to the ground plane similarly to what is shown in figure 19. the evaluation board shown in figure 19 is available from analog devices, inc. upon request. 12961-019 figure 19. EV1HMC1118LP3D evaluation pcb table 8. bill of materials for the EV1HMC1118LP3D evaluation board 1 item description manufacturer 2 j1 to j3 pc mount sma rf connectors tp1 to tp5 through-hole hold mount test points c1, c5 100 pf capacitors, 0402 package u1 hmc1118 spdt switch analog devices, inc. pcb 600-01012-00-1 evaluation pcb, rogers 4350 circuit board material EV1HMC1118LP3D , analog devices, inc. 1 1 reference this number to order the full evaluation pcb. 2 the blank cells in the manufacturer column are left blank intentionally for they are user-selectable.
pr o duct overview o nline documentation design resources discussion sample & buy data sheet hmc1118 rev. 0 | page 11 of 11 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.92 1.70 sq 1.48 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r * 0.35 0.30 0.25 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.95 0.85 0.75 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-08-2015-a pkg-000000 * compliant with jedec standards mo-220-veed-4 with the exception of package edge to lead edge. figure 20. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-38) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 hmc1118lp3de ?40c to +85c msl3 16-lead lead frame chip scale package [lfcsp] cp-16-38 xxx x 1118h hmc1118lp3detr ?40c to +85c msl3 16-lead le ad frame chip scale package [lfcsp] cp-16-38 xxx x 1118h EV1HMC1118LP3D evaluation board 1 hmc1118lp3de and h mc1118lp3detr are rohs -compliant parts. 2 see the absolute maximum ratings section. 3 xxxx is the 4-digit lot number. ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12961-0-10/15(0)

▲Up To Search▲

Price & Availability of EV1HMC1118LP3D

	To Download EV1HMC1118LP3D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .